1. Field of the Invention
The present invention relates to semiconductor devices and manufacturing methods thereof, and particularly to an MOSFET having a gate electrode formed of metal film and a manufacturing method thereof.
2. Description of the Background Art
Polycide gates having stacked structure of polysilicon film and metal silicide film are widely used as the gate electrodes of MOSFETs. However, formation of the gate electrodes with metal film, such as tungsten film, is effective to reduce the gate resistance so as to realize higher-speed operation of the MOSFETs.
When a gate electrode is formed of metal film, heat treatment after the formation of the gate electrode is restricted because of the low thermal resistance of the metal film and some other reasons. For example, the heat treatment to the source/drain regions which are usually formed after the formation of the gate electrode is restricted and the dopant is insufficiently activated, and then the source/drain resistance is increased to lower the driving capability of the MOSFET. To solve this inconvenience, a method of forming the source/drain regions before formation of the gate electrode is suggested, in which a dummy electrode is formed for the gate electrode (the replace method).
FIG. 36 is a sectional view showing the structure of an MOSFET having a gate electrode formed by a conventional replace method (Ext. Abst. of International Electron Devices Meeting 1998, pp.785-788). The conventional MOSFET shown in FIG. 36 has a semiconductor substrate 101, a trench-type element isolation structure 102 formed in the element isolation region in the main surface of the semiconductor substrate 101, a pair of source/drain regions 103 selectively formed in the element formation region in the main surface of the semiconductor substrate 101 to face each other through the channel region, a silicon oxide film 104 formed on the trench-type element isolation structure 102 and on the source/drain regions 103 through a silicon oxide film 108, a gate insulating film 105 formed on the main surface of the semiconductor substrate 101 in the part in which the silicon oxide film 104 is not formed in the element formation region, and a gate electrode 106 formed to fill the recessed portion formed by sides of the silicon oxide film 104 and the upper surface of the gate insulating film 105.
FIGS. 37 to 42 are sectional views showing a method for manufacturing the MOSFET shown in FIG. 36 in the order of process steps. First, the trench-type element isolation structure 102 filled with insulating film is formed in the element isolation region in the main surface of the semiconductor substrate 101 which is composed of single crystal silicon. Next, to form a well and to adjust the operation threshold voltage of the MOSFET, boron ions 107 are implanted into the semiconductor substrate 101 by an ion implantation (FIG. 37).
Next, the silicon oxide film 108 is formed by a thermal oxidation on the main surface of the semiconductor substrate 101. Subsequently, a polysilicon film and a silicon nitride film are formed in this order by CVD on the silicon oxide film 108. After this, the polysilicon film and the silicon nitride film are patterned into given shape by photolithography and anisotropic dry etching to selectively form a dummy electrode 150 on the silicon oxide film 108; the dummy electrode 150 has a stacked structure in which the polysilicon film 109 and the silicon nitride film 110 are stacked in this order (FIG. 38).
Next, arsenic ions 111 are implanted into the semiconductor substrate 101 by an ion implantation to form the source/drain regions 103 in the main surface of the semiconductor substrate 101 (FIG. 39). Subsequently, a thermal treatment is performed to activate the implanted arsenic ions 111. Next, a silicon oxide film is formed on the entire surface by a CVD. After that, the silicon oxide film is polished by CMP (Chemical Mechanical Polishing) until the upper surface of the dummy electrode 150 is exposed to form the silicon oxide film 104 (FIG. 40). Next, the dummy electrode 150 and the silicon oxide film 108 under the dummy electrode 150 are removed (FIG. 41). In FIG. 41, the silicon oxide films 104 and 108 serve as a mold for forming the gate electrode.
Next, the gate insulating film 105 composed of silicon oxide film is formed on the main surface of the semiconductor substrate 101 by a thermal oxidation. Subsequently, a tungsten film 113 is formed all over the surface by CVD or sputtering (FIG. 42). Next, by the CMP method, the tungsten film 113 is polished until the upper surface of the silicon oxide film 104 is exposed, thus providing the structure shown in FIG. 36.
FIG. 43 is a sectional view showing the structure of another MOSFET having a gate electrode formed by a conventional replace method. (Ext. Abst. of International Electron Devices Meeting 1998, pp.777-780). The conventional MOSFET shown in FIG. 43 has the semiconductor substrate 101 and the trench-type element isolation structure 102 which are the same as those in the MOSFET shown in FIG. 36, a pair of extensions 121 and source/drain regions 122 selectively formed in the element formation region in the main surface of the semiconductor substrate 101 to face each other with the channel region therebetween, a silicon oxide film 123 formed on the trench-type element isolation structure 102 and on the extensions 121 with a silicon oxide film 127 interposed therebetween, sidewalls 124 formed in sides of the silicon oxide film 123, a gate insulating film 125 formed on the main surface of the semiconductor substrate 101 in the part in which the silicon oxide film 123 and the sidewalls 124 are not formed in the element formation region, and a gate electrode 126 formed to fill the recessed part formed by the sides of the sidewalls 124 and the upper surface of the gate insulating film 125.
FIGS. 44 to 50 are sectional views showing a method of manufacturing the MOSFET shown in FIG. 43 in the order of processes. First, by the same method as that described above, the same structure as that shown in FIG. 37 is obtained. Subsequently, the silicon oxide film 127 is formed on the main surface of the semiconductor substrate 101 by a thermal oxidation. Next, by CVD, a polysilicon film is formed on the silicon oxide film 127. Then, the polysilicon film is patterned into given shape by photolithography and anisotropic dry etching to selectively form a dummy electrode 128 composed of polysilicon film on the silicon oxide film 127 (FIG. 44).
Next, arsenic ions 129 are implanted by an ion implantation into the semiconductor substrate 101 to form the extensions 121 in the main surface of the semiconductor substrate 101 (FIG. 45). Next, a silicon nitride film is formed on the entire surface by a CVD. Subsequently, the silicon nitride film is etched by an anisotropic dry etching to form the sidewalls 124 composed of the silicon nitride film on the sides of the dummy electrode 128. After that, arsenic ions 130 are implanted into the semiconductor substrate 101 by an ion implantation to form the source/drain regions 122 which are deeper than the extensions 121 (FIG. 46). Then a thermal treatment is applied to activate the implanted arsenic ions 130.
Next, a silicon oxide film is formed all over the surface by a CVD. Next, the silicon oxide film is polished by CMP until the upper surface of the dummy electrode 128 is exposed to form the silicon oxide film 123 (FIG. 47). Next, the dummy electrode 128 and the silicon oxide film 127 under the dummy electrode 128 are removed (FIG. 48). In FIG. 48, the silicon oxide films 123 and 127 and the sidewalls 124 serve as a mold for forming the gate electrode.
Next, the gate insulating film 125 composed of silicon oxide film is formed on the main surface of the semiconductor substrate 101 by a thermal oxidation. After that, a tungsten nitride film 131 and a tungsten film 132 are formed in this order by CVD or sputtering on the entire surface (FIG. 49). Next, by photolithography, a photoresist 133 having a given pattern is formed on the tungsten film 132. After this, the tungsten nitride film 131 and the tungsten film 132 are etched by an anisotropic dry etching to form the gate electrode 126 made of the tungsten nitride film 134 and the tungsten film 135 (FIG. 50). As shown in FIG. 50, the side ends of the gate electrode 126 extend on the silicon oxide film 123. Next, the photoresist 133 on the tungsten nitride film 135 is removed to obtain the structure shown in FIG. 43.
These conventional semiconductor devices and manufacturing methods have the following problems. First, while reducing the channel length is effective to enhance the driving capability of the MOSFET so as to increase the operating speed, the channel length in the conventional semiconductor device and manufacturing method shown in FIGS. 36 and 43, for example, is approximately equal to the gate length of the dummy electrode 150. Accordingly, since the channel length is defined by the minimum resolution limit in the photolithography technique adopted when forming the dummy electrode 150, it is difficult to reduce the channel length. Furthermore, if the dummy electrode is simply downsized to reduce the channel length, it will raise the problem that the gate resistance of the gate electrode increases.
Moreover, as shown in FIG. 36, for example, the upper surface of the gate electrode 106 composed of metal film is exposed in the conventional semiconductor device and its manufacturing method. Hence, when forming a contact hole to make electrical contact with the source/drain regions, the self-aligned contact formation technique cannot be used to avoid contact between the gate electrode and the contact hole.
According to a first aspect of the present invention, a semiconductor device comprises: a substrate; source/drain regions formed in a main surface of the substrate with a channel region interposed therebetween; a gate insulating film formed on the main surface of the substrate in an area in which the channel region is formed; and an inversely tapered gate electrode formed on an upper surface of the gate insulating film.
According to a second aspect of the present invention, a semiconductor device comprises: a substrate; source/drain regions formed in a main surface of the substrate with a channel region interposed therebetween; a first insulating film formed on the main surface of the substrate in an area in which the source/drain regions are formed; sidewalls composed of a second insulating film and formed on sides of the first insulating film; a gate insulating film composed of a third insulating film and formed on the main surface of the substrate in an area in which the channel region is formed; and a gate electrode formed to fill an inversely tapered recessed portion formed by sides of the sidewalls and an upper surface of the gate insulating film.
Preferably, according to a third aspect of the invention, in the semiconductor device, the third insulating film is composed of a material having a larger dielectric constant than silicon oxide film.
Preferably, according to a fourth aspect of the invention, in the semiconductor device, the third insulating film is formed to extend only onto the sides of the sidewalls.
Preferably, according to a fifth aspect of the invention, the semiconductor device further comprises an impurity region locally formed in the substrate only under the gate insulating film and having a conductivity type which is opposite to that of the source/drain regions.
Preferably, according to a sixth aspect of the invention, in the semiconductor device, the source/drain regions are formed in the main surface of the substrate also in areas in which the sidewalls are formed, and the semiconductor device further comprises an impurity region locally formed in the substrate only under the gate insulating film and the sidewalls and having a conductivity type which is opposite to that of the source/drain regions.
Preferably, according to a seventh aspect of the invention, the semiconductor device further comprises a fourth insulating film formed on an upper surface of the gate electrode and surrounding the gate electrode with the sidewalls, wherein the second and fourth insulating films are composed of a material which is different from that of the first insulating film.
Preferably, according to an eighth aspect of the invention, in the semiconductor device, the gate electrode has its peripheral part formed to extend on an upper surface of the first insulating film.
According to a ninth aspect of the present invention, a method for manufacturing a semiconductor device comprises the steps of: (a) forming a structure on a main surface of a substrate in an area in which a gate electrode is formed later; (b) forming source/drain regions in the main surface of the substrate in an area in which the structure is not formed; (c) forming a first insulating film on the main surface of the substrate in an area in which the structure is not formed; (d) after the step (c), removing the structure; (e) forming a second insulating film on the construction obtained by the step (d) and etching the second insulating film by an anisotropic etching whose etching rate is higher in depth direction of the substrate to form sidewalls on sides of the first insulating film; (f) forming a gate insulating film composed of a third insulating film on the main surface of the substrate in an area in which the first insulting film and the sidewalls are not formed; and (g) forming the gate electrode to fill an inversely tapered recessed part formed by sides of the sidewalls and an upper surface of the gate insulating film.
Preferably, according to a tenth aspect of the invention, in the semiconductor device manufacturing method, in the step (a), the structure is formed by stacking a first film composed of a material which is different from that of the second insulating film and a second film composed of a material which is different from that of the first insulating film in this order, and the step (d) comprises the steps of; (d-1) between the step (c) and the step (e), removing the second film with the first film left unremoved, and (d-2) between the step (e) and the step (f), removing the first film by a wet etching.
Preferably, according to an eleventh aspect of the invention, in the semiconductor device manufacturing method, in the step (a), the structure is formed with a material which is different from that of the first insulating film, and in the step (d), the structure is removed by a wet etching.
Preferably, according to a twelfth aspect of the invention, in the semiconductor device manufacturing method, in the step (f), the third insulating film is formed with a material having a larger dielectric constant than silicon oxide film.
Preferably, according to a thirteenth aspect of the invention, in the semiconductor device manufacturing method, the step (f) comprises the steps of, (x-1) forming the third insulating film on the construction obtained by the step (e), and (x-2) removing the third insulating film formed on an upper surface of the first insulating film.
Preferably, according to a fourteenth aspect of the invention, in the semiconductor device manufacturing method, the step (g) comprises the steps of; (y-1) after the step (x-1), forming a conductor film which is a material of the gate electrode on the third insulating film, and (y-2) after the step (y-1), thinning the conductor film until the upper surface of the first insulating film is exposed to form the gate insulating film, and the step (x-2) is performed together in the process in which the step (y-2) is performed.
Preferably, according to a fifteenth aspect of the invention, in the semiconductor device manufacturing method, the step (g) comprises the steps of; (z-1) after the step (x-1), forming a conductor film which is a material of the gate electrode on the third insulating film, and (z-2) between the step (z-1) and the step (x-2), thinning the conductor film until the third insulating film formed on the upper surface of the first insulating film is exposed to form the gate electrode, and in the step (x-2), the third insulating film is removed by etching the third insulating film exposed in the step (z-2).
Preferably, according to a sixteenth aspect of the invention, the semiconductor device manufacturing method further comprises the step of: (h) between the step (e) and the step (f), introducing an impurity into the substrate by using the first insulating film and the sidewalls as masks to form an impurity region having a conductivity type which is opposite to that of the source/drain regions.
Preferably, according to a seventeenth aspect of the invention, in the semiconductor device manufacturing method, in the step (b), the source/drain regions are formed to extend also under peripheral part of the structure in the main surface of the substrate, and the manufacturing method further comprises the step of: (i) between the step (d) and the step (e), introducing an impurity into the substrate by using the first insulating film as a mask to form an impurity region having a conductivity type which is opposite to that of the source/drain regions.
Preferably, according to an eighteenth aspect of the invention, in the semiconductor device manufacturing method, the first insulating film is composed of a material which is different from that of the second insulating film, and the manufacturing method further comprises the steps of; (j) removing the gate electrode for a given film thickness from its upper surface, and (k) after the step (j), forming a fourth insulating film composed of a material which is different from that of the first insulating film on the gate electrode.
Preferably, according to a nineteenth aspect of the invention, in the semiconductor device manufacturing method, the step (g) comprises the steps of; (g-1) forming a conductor film which is a material of the gate electrode on the construction obtained by the step (f), and (g-2) patterning the conductor film to form the gate electrode having its peripheral part extending on an upper surface of the first insulating film.
According to the first aspect of the present invention, the gate length in the upper part of the gate electrode is longer than that in its lower part, so that the gate resistance can be reduced without enlarging the channel length.
According to the second aspect of the invention, reflecting the shape of the sidewalls, the gate length in the upper part of the gate electrode is longer than that in its lower part. Hence the gate resistance can be reduced without enlarging the channel length.
According to the third aspect of the invention, the gate insulating film capacitance can be larger than that in a semiconductor device having a gate insulating film formed of a silicon oxide film, so that the driving capability of the semiconductor device can be enhanced.
According to the fourth aspect of the invention, the third insulating film is not formed on the upper surface of the first insulating film. Accordingly, when source/drain wiring is formed in the first insulating film to make electrical contact with the source/drain regions, it is possible to avoid the trouble that the wiring capacitance of the source/drain wiring increases due to the third insulating film.
According to the fifth aspect of the invention, it is possible to reduce the junction capacitance caused by the junction between the source/drain regions and the impurity region.
According to the sixth aspect of the invention, it is possible to reduce the junction capacitance caused by the junction between the source/drain regions and the impurity region. Furthermore, the opposite conductivity types cancel each other in the part in which the impurity region and the source/drain regions overlap. As a result, the depth of the source/drain regions becomes shallower under the sidewalls, thus further effectively suppressing the short-channel effect.
According to the seventh aspect of the invention, the gate electrode is surrounded by the second and fourth insulating films made of a different material from that of the first insulating film. Hence, the self-aligned contact formation technique can be used when forming a contact hole in the first insulating film.
According to the eighth aspect of the invention, the gate length in the upper part of the gate electrode can be still longer to further reduce the gate resistance.
According to the ninth aspect of the invention, reflecting the shape of the sidewalls, the gate length in the upper part of the gate electrode is longer than that in its lower part. Hence the gate resistance can be reduced without enlarging the channel length under the gate insulating film.
According to the tenth aspect of the invention, in the step (d-1), only the second film can be removed without removing the first insulating film. In the step (d-2), only the first film can be removed without removing the sidewalls. Furthermore, the main surface of the substrate can be protected from damage when removing the first film.
According to the eleventh aspect of the invention, only the structure can be removed without removing the first insulating film. Furthermore, the main surface of the substrate can be protected from damage when removing the structure.
According to the twelfth aspect of the invention, the gate insulating film capacitance can be larger than that of a gate insulating film formed of a silicon oxide film, so that the driving capability of the semiconductor device can be enhanced.
According to the thirteenth aspect of the invention, the third insulating film formed on the upper surface of the first insulating film in the step (x-1) is removed in the step (x-2). Accordingly, when source/drain wiring for making electric contact with the source/drain regions is formed in the first insulating film, it is possible to prevent the wiring capacitance of the source/drain wiring from increasing due to the third insulating film.
According to the fourteenth aspect of the invention, the third insulating film can be removed at the same time in the process of thinning the conductor film for forming the gate electrode. Hence, the third insulating film formed on the upper surface of the first insulating film can be removed without increasing the number of manufacturing process steps.
According to the fifteenth aspect of the invention, the process of thinning the conductor film is stopped when the third insulating film is exposed, and the third insulating film formed on the upper surface of the first insulating film is removed by etching. Accordingly, the upper part of the gate electrode having a longer gate length is not removed in the thinning process, and therefore the gate resistance can be further reduced.
According to the sixteenth aspect of the invention, an impurity region having an opposite conductivity type to that of the source/drain regions and for adjusting the operation threshold voltage of the semiconductor device can be locally formed in the substrate only under the gate insulating film. Hence junction capacitance caused by the junction between the source/drain regions and the impurity region can be reduced.
According to the seventeenth aspect of the invention, an impurity region having an opposite conductivity type to that of the source/drain regions and for adjusting the operation threshold voltage of the semiconductor device can be locally formed in the substrate only under the gate insulating film and the sidewalls. Hence junction capacitance caused by the junction between the source/drain regions and the impurity region can be reduced. Furthermore, the opposite conductivity types cancel each other in the part in which the impurity region and the source/drain regions overlap. As a result, the depth of the source/drain regions under the sidewalls becomes shallower and the effect of suppressing the short-channel effect is enhanced.
According to the eighteenth aspect of the invention, the gate electrode can be surrounded by the second and fourth insulating films formed of a different material from that of the first insulating film. Accordingly, the self-aligned contact formation technique can be used when forming a contact hole in the first insulating film.
According to the nineteenth aspect of the invention, the gate length in the upper part of the gate electrode can be still longer to further reduce the gate resistance.
The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a semiconductor device in which the channel length can be reduced without increasing the gate resistance so that the driving capability of MOSFET can be improved to realize higher-speed operation and a manufacturing method thereof, and to obtain a semiconductor device having a gate electrode which allows the use of the self-aligned contact formation technique and its manufacturing method.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.